1. Technical Field
The present invention relates to semiconductor processing, and more particularly to devices and methods for forming accurate extension diffusion regions that include a controllable junction depth and have a lateral overlap into a channel region.
2. Description of the Related Art
As dimension size diminishes for semiconductor processing, dimensional restrictions are more difficult to achieve and verify. For example, processing activities like doping a substrate may often lead to dopants existing in unwanted areas. This is particularly true in a channel region of field effect transistors. The field effect transistors often undergo a plurality of doping or implantation steps. These may include forming a channel below a gate, forming halo diffusion regions, forming diffusion regions for sources and drains and extending the source and drain diffusion regions below the gate electrodes (extensions).
In many instances, these diffusion steps can cause surface damage to a surface of a semiconductor substrate. In addition the uncertainties related to the diffusion steps, related etching steps are difficult to control as well. Diffusion regions and related structure are therefore difficult to maintain and control dimensionally during and after processing. With shallow junctions, these difficulties are amplified given the smaller sizes involved.